Modern microprocessors integrate on-chip (on-die) cache memory as an efficient means of achieving high performance memory access. On-chip cache provides high-speed, temporary data storage that the microprocessor can access more quickly than off-chip memory. The trend in microprocessor performance improvement is to incorporate ever more cache memory and to configure the cache in multiple (hierarchical) levels (e.g., L1 and L2).
Traditionally, on-chip cache memory has been implemented using Static Random Access Memory (SRAM) because SRAM has very high access speed and low latency. But because each bit of SRAM typically requires six transistors (6T), the size of on chip caches have been limited in order to maintain reasonable die size and manufacturing cost.
One alternative to SRAM is Dynamic Random Access Memory (DRAM). DRAM has a simpler cell structure than SRAM, but requires regular access (refresh) to maintain the data in each storage cell. One common type of DRAM is a 1T-1C DRAM that uses a cell made from one transistor (e.g., a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)) and one capacitor. The capacitor is used to store a data bit in the form of an electronic charge, and the transistor provides read and write access to the charge held in the capacitor. The transistor is often referred to as the “access” transistor or the “transfer device” of the DRAM cell. This cell is typically about one-tenth the size of a 6T SRAM cell. However, this type of DRAM may require special processing steps to make capacitors that can store enough charge to maintain reasonable refresh times (e.g., at least 25 fF). The special processing steps are not typically used in the fabrication of microprocessors. The capacitor may also limit the scalability of the traditional DRAM structure.